JPMorgan Analyzes Taiwan Semiconductor: CoWoS Shor

JPMorgan Analyzes Taiwan Semiconductor: CoWoS Shortfall Widens to 20%, AI CPUs Take Over from GPUs

Public disclosures from Taiwan Semiconductor confirm a continuous expansion of its advanced packaging capabilities, particularly CoWoS and SoIC. The company projects that CoWoS capacity will achieve a compound annual growth rate (CAGR) surpassing 80% from 2022 through 2027.

Capacity has been raised to approximately 220,000 wafers per month—so why is it still insufficient?

According to supply chain channel checks by JPMorgan, Taiwan Semiconductor's internal CoWoS monthly capacity is projected to reach approximately 115,000 wafers by the end of 2026, scale up to roughly 190,000 wafers by 2027, and hit between 220,000 and 225,000 wafers by the close of 2028.

Secondary reports on these estimates show minor discrepancies; for instance, some sources note that JPMorgan's earlier forecasts placed end-2027 capacity at 175,000 wafers per month and end-2028 capacity at 220,000 wafers per month. Because TSMC does not officially disclose these metrics, these figures represent potential "upside" targets in supply chain models rather than definitive, guaranteed production volumes.

OSAT providers are increasingly stepping in to supplement the supply chain. Advanced packaging capacity similar to CoWoS from players like ASE Group and Amkor is projected to ramp from roughly 12,000–15,000 wafers per month at the end of 2026 to around 85,000 wafers per month by the end of 2028. Concurrently, Taiwan Semiconductor is optimizing its own production lines, reallocating internal resources by shifting some capacity originally slated for SoIC to aggressively accelerate its CoWoS expansion.

The underlying challenge is that AI hardware is becoming increasingly packaging-intensive. Next-generation AI accelerators, specialized AI CPUs, and custom ASICs are consuming a larger share of advanced packaging capacity; many newer architectures feature expanded die areas, which inherently limits the number of chips yielded per wafer and drains more production resources per unit. Consequently, even as manufacturing lines scale up, the actual footprint and capacity consumed on a per-chip basis are rising simultaneously.

Furthermore, the projected ~20% supply-demand deficit is not a universally accepted market consensus. For instance, TrendForce reported in June that this gap could contract to roughly 10% by the end of 2026. Their model estimates Taiwan Semiconductor's standalone monthly capacity will reach 120,000–140,000 wafers by 2026, supplemented by an additional 50,000–60,000 wafers per month from OSAT partners. The variance between these supply chain assessments ultimately boils down to differing calculations regarding how fast customer demand is scaling and how efficiently outsourced, external packaging lines can be brought online to deliver viable commercial yields.

NVIDIA remains the largest customer, and CPUs are now also joining the queue.

NVIDIA remains the dominant driver of advanced packaging demand within JPMorgan’s modeling. By 2028, its annual CoWoS requirement is projected to climb to roughly 1.735 million wafers, marking a substantial leap from 2027 levels. This massive capacity consumption is propelled not just by next-generation GPUs, but also by a broader hardware portfolio including the Vera and Rosa AI CPUs, LPUs, and advanced networking systems like the Spectrum-X CPO (Co-Packaged Optics) switches. In terms of technology allocation, the model assumes that NVIDIA’s primary accelerators and CPO hardware will utilize CoWoS-L, whereas its CPUs and LPUs will predominantly adopt CoWoS-R, with production volumes split across Taiwan Semiconductor, Amkor, and ASE Group.

This represents a major paradigm shift in AI infrastructure architecture. Traditional data center supply chain analyses focused almost exclusively on the "GPU plus HBM" bottle-neck; today, AI CPUs themselves are demanding ultra-high memory bandwidth, denser interconnect architectures, and optimized system efficiency. As a result, host processors are now actively competing for cutting-edge packaging capacity.

Meanwhile, designs related to the upcoming Feynman architecture have not yet been fully finalized. Wall Street supply chain models currently omit any explicit assumptions for CoPoS integration; near-term roadmaps suggest a continued reliance on standard CoWoS-L coupled with partial SoIC logic stacking. Even as alternative architectural packaging technologies debut down the road, bypassing CoWoS entirely will remain highly impractical for mainstream AI accelerators throughout the 2027–2028 cycle.

AMD, TPUs, and Trainium are all competing for capacity—shortages are not exclusive to NVIDIA.

Evaluating the advanced packaging crunch through the lens of NVIDIA alone severely understates the scope of the current supply squeeze. Demand for CoWoS and equivalent advanced packaging technologies is simultaneously accelerating across a broader ecosystem, notably from AMD, Google’s TPU program, and Amazon’s Trainium accelerators.

> AMD: The chipmaker is facing capacity constraints across both its datacenter CPUs and AI accelerators. Next-generation products like the Venice server CPU, MI450, and MI500 are all modeled to consume significantly more advanced packaging allocation. The MI500, in particular, features an expanded physical package size, inherently requiring more wafer real estate and packaging resources per chip. Consequently, while AMD’s total wafer-level fan-out demand is projected to climb through 2027 and 2028, actual supply fulfillment rates may only hit 50% to 60%.

> Google TPUs: Google's custom silicon volume continues to scale. Total TPU shipment forecasts for 2027 have been revised upward, with the MediaTek-co-designed v8 series driving the bulk of this incremental growth before the product cycle transitions to the v9 generation in 2028. While certain future TPU iterations are slated to potentially diversify into Intel’s EMIB-T packaging architecture, this secondary supply pipeline remains bottlenecked by substrate shortages and yield maturity.

> Amazon Trainium: AWS's custom AI infrastructure is similarly accelerating. Full-lifecycle demand projections for Trainium3 have been adjusted upward, with a portion of the design and order allocation potentially spilling over to Marvell. Looking further out, Trainium4 is expected to begin its production ramp in 2028, introducing 3D SoIC logic stacking alongside sophisticated interconnect frameworks. However, these specific shipment volumes and architectural roadmaps remain model-driven assumptions that depend on final tape-outs and manufacturing execution.

Ultimately, this multi-front demand explains why the market remains anxious about a structural supply deficit despite Taiwan Semiconductor's aggressive capacity expansions. The advanced packaging bottleneck is no longer just a reflection of NVIDIA GPU volume; it is being compounded by hyperscaler ASICs, high-performance AI CPUs, and expanding chiplet footprints that collectively drain available foundry resources.

Taiwan Semiconductor’s total CoWoS consumption is projected to reach approximately 1.24 million, 2.38 million, and 2.63 million wafers per year in 2026, 2027, and 2028, respectively, with NVIDIA maintaining the largest share while AMD and Broadcom/TPU contribute greater incremental volume.

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