Nvidia’s adoption of Co-Packaged Optics (CPO) in its upcoming Vera Rubin AI chip platform hinges on the semiconductor testing supply chain, as the most difficult hurdle to mass production is wafer-level testing of the ‘Electronics-on-Top, Photonics-on-Bottom’ structure, which is a 3D stack of chips, like a sandwich, that uses TSMC’s SoIC advanced packaging technology, media report. The issue is testing for photonic and electrical signals differs significantly, and the industry does not have testing equipment able to do mass production volumes. If a solution cannot be found, it may hurt adoption of the technology. A number of companies are rushing to develop such equipment, including Advantest, Teradyne, FormFactor, MPI and Hermes Testing (HTSI). $NVIDIA(NVDA.US) $Teradyne(TER.US) $Formfactor(FORM.US) $6857 #semiconductors #semiconductor

Source: Dan Nystedt