ASE is speeding up panel-level-packaging (PLP) for high-end AI chips amid hot demand, with its first fully automated 310 x 310mm PLP production line up by end-2026, media report. PLP (or Fan-out PLP, FOPLP) is gaining steam, with rival Powertech doing 510 x 515mm PLP for major clients AMD and Broadcom, while TSMC’s PLP is called CoPoS (Chip on Panel on Substrate). 1/2 $Advanced Semiconductor Engineering(ASX.US) $AMD(AMD.US) $Broadcom(AVGO.US) $Taiwan Semiconductor(TSM.US) #semiconductors
Source: Dan Nystedt
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