TSMC has local competition for new advanced semiconductor packaging technology it calls CoPoS (Chip-on-Wafer-on-Substrate), which is to be used on the latest AI chips from Nvidia, AMD, media report, as packaging giant ASE has a 300x300mm FOPLP (Fan-out Panel Level Packaging) technology production line as well, and Powertech Technology achieved mass production in 2019 of its FOPLP technique, called PiFO (Pillar integration Fan-Out). $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) $NVIDIA(NVDA.US) $AMD(AMD.US) $Broadcom(AVGO.US) #semiconductors #semiconductor #FOPLP
Source: Dan Nystedt
The copyright of this article belongs to the original author/organization.
The views expressed herein are solely those of the author and do not reflect the stance of the platform. The content is intended for investment reference purposes only and shall not be considered as investment advice. Please contact us if you have any questions or suggestions regarding the content services provided by the platform.
