TSMC's "Mr. CoWoS": ABF Substrate Shortage May Be Second Only to Memory in Coming Years

Taiwan Semiconductor continues to expand its advanced packaging capacity, narrowing the CoWoS supply-demand gap, but supply chain bottlenecks are shifting from memory to substrate materials.

He Jun, Vice President of Advanced Packaging at Taiwan Semiconductor—known in the industry as "Mr. CoWoS"—stated that the shortage of ABF substrates may be second only to memory in the coming years, becoming the second-largest bottleneck in the advanced packaging supply chain. Meanwhile, Taiwan Semiconductor's CoWoS capacity has doubled for three consecutive years, with current supply "very close" to market demand, though not yet fully meeting it.

As CoWoS capacity gradually catches up with demand, bottlenecks in advanced packaging are shifting upstream to materials. The increasing size and packaging complexity of AI accelerators are further driving up demand for ABF substrates, making them a key constraint on the expansion of advanced packaging.

CoWoS Supply-Demand Gap Narrows, 14x Reticle Solution Expected Before 2029

He Jun stated that Taiwan Semiconductor's CoWoS capacity has doubled annually for three consecutive years, with current supply very close to market demand. The 5.5x reticle size CoWoS has achieved mass production, with yields exceeding 98% in products for multiple AI customers; according to the technology roadmap, the 14x reticle size CoWoS is expected to launch before 2029.

As packaging sizes increase, supply chain requirements for materials and manufacturing precision are rising in tandem. He Jun pointed out that when packaging sizes exceed 3x reticle size, quality standards for all components must reach automotive-grade levels to keep failure rates within an acceptable range.

ABF Substrates Replace Memory as New Bottleneck in Advanced Packaging

On the supply chain front, He Jun expects that the shortage of ABF substrates will be second only to memory in the coming years, becoming the second-largest bottleneck in advanced packaging. Customers have begun sourcing substrates from multiple suppliers to ensure supply, but differences in thermal and mechanical properties among suppliers pose new challenges to manufacturing consistency.

Meanwhile, Taiwan Semiconductor is accelerating the development of its SoIC hybrid bonding technology. The technology achieved mass production with a 6-micron pitch last year and is planned to shrink further to 4.5 microns before 2029 for application in A14 chip stacking. He Jun stated that SoIC interconnect density can reach 50 times that of traditional solutions, with energy efficiency improved by approximately 5 times.

Chiplet Smart Pairing: Advanced Packaging Moves Toward System-Level Synergy

As packaging complexity increases, Taiwan Semiconductor is using Chiplet "smart pairing" technology to recombine chiplets with complementary performance, reducing waste caused by performance variations in individual chips and improving overall yield and effective output.

The function of interposers is also evolving from simple interconnection to integration, potentially carrying voltage regulators, capacitors, and silicon photonics devices in the future. Meanwhile, Taiwan Semiconductor is promoting parallel development among customers, suppliers, and foundries, issuing system specification guidelines six quarters before mass production and requiring suppliers to configure R&D teams near foundries to accelerate collaborative solutions for thermal, mechanical, and power consumption issues.

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