Global debut! Intel showcases ZAM memory prototype: single chip 512GB, power consumption cut in half, directly competing with HBM

Intel's next-generation AI memory technology Z-Angle Memory (ZAM), developed in collaboration with SoftBank, has made its global debut. This new technology, aimed at challenging the dominance of the high bandwidth memory (HBM) market, showcases significant performance advantages. The product features a vertical stacking architecture, promising to greatly enhance capacity while reducing power consumption.

On Wednesday, according to Wccftech, early data indicates that ZAM can reduce power consumption by 40% to 50%, with a single chip capacity of up to 512GB, and simplifies the production process through Z-Angle interconnect technology. These features make it a potential solution to the current energy consumption bottlenecks in AI applications and supply chain constraints.

SoftBank's subsidiary SAIMEMORY first showcased the ZAM prototype at the Intel Connection Japan 2026 event on February 3. Intel revealed in a blog post that the prototype is planned for release in 2027, with full commercialization expected by 2030.

Dr. Joshua Fryman, Chief Technology Officer of Intel's Government Technology Division and an Intel Fellow, attended the event. SAIMEMORY was co-founded by SoftBank, Intel, and the University of Tokyo in December 2024 and officially began operations in June 2025, with Hideya Yamaguchi serving as the current President and CEO.

Vertical Stacking Breaks Through Thermal Bottlenecks

According to PC Watch, traditional memory uses a planar stacking structure, but this design is nearing its limits due to power consumption and thermal constraints. Current designs have pushed 16-layer stacking close to the maximum, with 20 layers considered the upper limit.

ZAM, named for its Z-axis, employs a design of vertically stacked chips. PC Watch points out that this design promises lower power consumption, higher capacity, and wider bandwidth compared to traditional DRAM. By vertically stacking, the heat generated by each chip can be evenly conducted upwards, addressing the long-standing thermal issues that have plagued planar stacking.

Wccftech cites Intel's statement that the main advantage of this architecture lies in its superior thermal management capabilities.

Technical Path Aiming at the Gap Between HBM and DDR

This new memory product is expected to utilize Intel's next-generation DRAM bonding (NGDB) technology. Information released by Sandia National Laboratories in January indicates that current high bandwidth memory often sacrifices capacity and other performance metrics for higher bandwidth.

The NGDB technology aims to eliminate this trade-off, bridging the gap between HBM and traditional DDR DRAM while providing significantly higher energy efficiency According to a press release from SoftBank, the prototype product of the ZAM project is expected to be completed in the fiscal year ending March 31, 2028, with commercialization targeted for the 2029 fiscal year. Dr. Joshua Fryman, an Intel Fellow, stated in the announcement that standard memory architectures cannot meet AI demands, and the new architecture and assembly methods developed by Intel enhance DRAM performance while reducing power consumption and costs.

PC Watch reported that SAIMEMORY emphasizes its strong partnerships, including collaborations with SoftBank and Intel, as well as a network of domestic and international investors and supply chain partners. This suggests that Intel may not be SAIMEMORY's only global partner.

This collaboration between SoftBank and Intel aims to carve out new paths in a market landscape dominated by HBM, directly addressing the energy consumption bottlenecks and supply chain challenges currently faced by AI.

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