A comprehensive understanding of NVIDIA's next-generation chip packaging technology "CoWoP"

Recently, the chip wafer-level packaging (CoWoP) technology that has been hotly discussed in the market differs from the existing CoWoS packaging. What impact does it have on the supply chain? What is its commercial outlook?

On August 5th, according to news from the Chasing Wind Trading Platform, JP Morgan stated in its latest research report that NVIDIA is exploring a revolutionary chip packaging technology, CoWoP (Chip-on-Wafer-on-PCB), which is expected to replace the existing CoWoS packaging solution.

JP Morgan pointed out that this technological change will utilize advanced high-density PCB (printed circuit board) technology to eliminate the ABF substrate layer in CoWoS packaging and directly connect the intermediary layer to the PCB.

The report also detailed the impact of "CoWoP" technology on the supply chain, believing that it is obviously negative news for ABF substrate manufacturers, but a significant opportunity for PCB manufacturers.

Although JP Morgan analysts believe that the probability of commercialization of this technology in the medium term is low, mainly due to multiple technical challenges, the report emphasized:

Regardless of whether CoWoP is successfully mass-produced, NVIDIA continues to lead innovation in data center AI infrastructure through a system-level approach.

CoWoP Technology Principles and Advantages/Disadvantages Analysis

The report states that CoWoP represents the Chip-on-Wafer-on-PCB technology path. After completing the manufacturing step of the chip-wafer intermediary layer, the intermediary layer (top with chip) is directly mounted onto the PCB (also known as platform PCB), rather than being bonded to the ABF substrate as in the CoWoS process.

The potential advantages of this technology include:

• Simplified system structure, improving data transmission efficiency by reducing transmission loss, ensuring higher range for NVLink interconnections;
• Better thermal management performance and lower power consumption;
• Reduced substrate costs that have been rising with each generation of products;
• Potential reduction of some backend testing steps.

However, JP Morgan believes that this technology faces key challenges. Currently, only Apple uses mSAP or SLP PCB technology, but its pitch size is larger and the PCB area is smaller, therefore scaling this technology to larger GPUs with higher current-carrying capacity remains a technical and operational challenge.

Supply Chain Impact: Significant Negative Impact on IC Substrates, Major Opportunities for PCB Manufacturers

JP Morgan stated in the report that for ABF substrate manufacturers, this is obviously negative news, as the added value of substrates may significantly decrease or completely disappear, with more complex and finely spaced signal routing shifting to the RDL layer (intermediary layer), while high-end PCB layers undertake the routing steps within the packaging.

JP Morgan believes that for PCB manufacturers, this is a significant opportunity for high-speed growth. The report pointed out:

"The trade-off between performance and the high current/voltage requirements of the motherboard is the main challenge preventing platform PCBs from achieving true substrate specifications. mSAP is the best PCB technology for achieving finer line/space dimensions of 25/25 microns, but it still falls far short of the sub-10 micron line/space capabilities of ABF."

Therefore, the firm believes that companies with advanced mSAP capabilities and in-depth knowledge of substrate/packaging processes will have a competitive advantage.

Low probability of commercialization in the medium term does not hinder NVIDIA's continued strengthening of innovation leadership

JP Morgan analysts believe that due to multiple technical challenges, the probability of CoWoP commercialization in the medium term remains low.

Historically, higher I/O counts and finer line/space dimensions (CoWoS-L down to 5 microns, CoWoS-S around 10 microns) required a transition to ABF substrates. For AI accelerators, even ABF substrates are expected to fail after 5/5 line/space dimensions.

PCB technology, even when using mSAP, can currently only achieve line/space widths of 20-30 microns, which is still significantly below the expected performance.

According to previous reports from Zhui Feng Trading Desk, Morgan Stanley also stated that the current line/space for high-density interconnect (HDI) PCBs is 40/50 microns, and even the substrate-like PCBs (SLP) used for iPhone motherboards only reach 20/35 microns, making it significantly challenging to reduce the PCB's line/space from 20/35 microns to below 10/10 microns.

Additionally, JP Morgan believes that NVIDIA's currently defined roadmap (developing towards CoWoS-L and CoPoS, adopting GPU sockets in the Cordelia Board) is quite contradictory to the new direction pursued by CoWoP.

Supply chain research shows that the participation of high-value-added packaging ecosystem players (such as TSMC) is low, mainly concentrated among PCB manufacturers and specific OSAT manufacturers, which reduces the likelihood of commercialization.

However, JP Morgan points out that regardless of whether CoWoP successfully achieves mass production, NVIDIA continues to lead innovation in data center AI infrastructure through a system-level approach.

"In the semiconductor field, NVIDIA was the first to launch CoWoS-L packaging, exploring CoWoP and CoPoS packaging technologies, and may lead the development of large-scale CPO (co-packaged optics) applications and 1.6T optical technology."

JP Morgan stated that this ongoing innovation capability is expected to allow NVIDIA to maintain its leading position in the GPU field in the coming years and dominate in competition with ASICs