Track Hyper | SK Hynix teams up with Intel to strike at the Nvidia empire?

Author: Zhou Yuan / Wall Street News

Recently, there have been reports in the industry that SK Hynix is expected to collaborate with Intel on HBM4 (sixth generation) memory supply. Does this mean that Intel is officially entering the competitive arena of the AI accelerator card market?

In the current context of exponentially growing computing power demand, the synergy between memory and chips has evolved from traditional hardware support to a core factor determining the competitiveness of AI systems.

Whether it is AI model training in large data centers or real-time inference in edge devices, memory performance has become a key variable limiting system efficiency, and the combination of HBM4 and Jaguar Shores aligns with industry development trends.

The performance bottleneck of AI chips has expanded from mere computing power to the data transmission phase.

Taking large language models based on the Transformer architecture as an example, the massive data generated during parameter updates in the training process needs to frequently interact between memory and processors. The serial transmission mode of traditional DDR memory results in data waiting time accounting for over 30%.

This phenomenon of idle computing resources is particularly evident when training models with hundreds of billions of parameters, often leading to insufficient effective computing hours per card per day.

HBM4 achieves parallel data transmission through a 2048-bit interface, increasing memory bandwidth to more than 1.5 times that of previous products. This architectural innovation directly addresses the contradiction of "fast computation, slow transmission" in AI chips.

In the field of image generation, AI accelerators using HBM4 memory can generate 512x512 resolution images approximately 40% faster than those using HBM3; in real-time inference of autonomous driving algorithms, the 30GB of data collected per second by vehicle sensors can be transmitted without delay through HBM4, providing valuable reaction time for decision-making systems.

More critically, the physical layer optimization of HBM4 employs CoWoS packaging technology, vertically stacking multiple DRAM chips and interconnecting them through Through-Silicon Vias (TSVs), significantly shortening the data transmission path.

This improvement in physical structure, combined with an optimized cache coherence protocol, significantly reduces memory latency, enhancing the response speed of AI chips when processing temporal data.

In AI prediction models for high-frequency trading, this low-latency characteristic can compress data processing response times to the microsecond level, providing more timely support for trading decisions.

For SK Hynix, this collaboration marks an important milestone in the commercialization of its HBM technology.

HBM4 faces fierce competition from Samsung and Micron. By partnering with Intel, SK Hynix can not only validate the adaptability of HBM4 in complex AI scenarios in advance but also leverage Intel's vast server customer resources to establish a scale production advantage.

Currently, SK Hynix's HBM4 production line in Icheon, South Korea, has initiated its second phase of expansion, with mass production expected in 2026, and the overall capacity will reach 300,000 wafers; it is still unclear what proportion of capacity will be accounted for by the collaboration orders with Intel.

Overall, Intel's demand should be more strategically urgent.

In the AI chip market, NVIDIA occupies over 70% market share with its CUDA ecosystem and H100/H200 series products (data source: Mercury Research) Jaguar Shores, as Intel's next-generation AI accelerator, urgently needs to achieve breakthroughs through hardware differentiation.

The introduction of HBM4 memory allows Jaguar Shores to reach industry-leading levels in memory bandwidth for the first time, providing a key advantage for entering the customized AI server market for cloud service providers.

Intel's Data Center Division has reached a preliminary agreement with Microsoft Azure to deploy AI server clusters equipped with Jaguar Shores and HBM4 by 2026, aimed at supporting the distributed training of large language models.

In the memory market, this collaboration intensifies the "Three Kingdoms" situation in the HBM field.

Samsung Electronics has announced plans to mass-produce HBM4 by the end of 2025, utilizing 12-layer stacking technology, which is 2 layers more than SK Hynix, claiming a potential bandwidth increase of 10%; Micron also plans to achieve technological breakthroughs in 2026, focusing on optimizing the power consumption performance of HBM4, with a target of improving energy efficiency by 25%.

The binding of SK Hynix and Intel may prompt Samsung to accelerate its collaboration with AMD, as both parties are already developing HBM4-based GPU prototypes; Micron is teaming up with Qualcomm to explore the application of HBM4 in mobile AI chips, attempting to carve out new market space.

Such intensity of competition may shorten the HBM technology iteration cycle from two years to within one year, potentially leading to the early start of HBM5 development in 2027.

The competitive dimensions of the AI chip market are changing.

NVIDIA's advantage lies in its complete software and hardware ecosystem, but with the proliferation of general technologies like HBM4, other manufacturers can narrow the performance gap in hardware.

Data center operators have begun to experiment with multi-vendor AI chip hybrid deployment solutions, with Google's TPU (Tensor Processing Unit, a custom AI acceleration card, belonging to the ASIC category) being used in hybrid clusters alongside NVIDIA GPUs in some operations.

If Intel can demonstrate cost-performance advantages through the Jaguar Shores + HBM4 combination, it is expected to break NVIDIA's monopoly in large-scale data centers.

Currently, Amazon AWS has indicated that it will conduct a six-month performance test on Jaguar Shores, covering several key metrics including model training speed, energy consumption ratio, and compatibility.

Although HBM4 can significantly enhance AI chip performance, it still faces developmental bottlenecks: first, the heat dissipation issues brought about by vertical stacking, with the thermal density of HBM4 chipsets reaching 150W/cm² during operation, exceeding the capabilities of traditional air cooling. Intel has developed a specialized immersion liquid cooling solution that directly contacts the chip surface with fluorinated liquid, significantly improving cooling efficiency compared to cold plate liquid cooling.

Second, the costs remain high, with the manufacturing cost of a single HBM4 chip being approximately 1.3 times that of HBM3E (data source: TrendForce), due to the increase in I/O count from 1024 to 2048, which complicates chip design, increases wafer size, and transforms the base chip into a logic chip, while also employing more advanced processes for producing logic chips For Intel, obtaining HBM4 is just the first step.

How to translate hardware performance into actual application advantages through software optimization (such as developing dedicated memory scheduling algorithms) and thermal innovation (such as integrated liquid cooling design) is the key to determining the success or failure of the Jaguar Shores market, and it is also the best footnote for whether Intel can truly gain a competitive ticket in the AI accelerator card market.

Intel's software team has developed a scheduling algorithm based on dynamic memory partitioning, which can automatically allocate bandwidth resources according to the memory requirements of different AI tasks, improving the training efficiency of the BERT (Bidirectional Encoder Representations from Transformers) model in tests.

SK Hynix also needs to collaborate with more chip manufacturers to promote HBM4 as an industry standard, avoiding the predicament of being "technologically advanced but ecologically isolated."

Currently, SK Hynix has reached a cooperation with TSMC to integrate HBM4 into the CoWoS packaging reference design, reducing the adaptation difficulty for other chip manufacturers.

The HBM4 collaboration between SK Hynix and Intel is not only about improving memory and chip performance but also signifies that future AI hardware competition will shift from a single technology contest to a comprehensive battle of ecosystem building and industrial chain integration.

The ultimate effectiveness of this collaboration will be validated in the reshuffling of the AI chip market over the next 2-3 years, and its impact will extend to the technological path choices and development pace of the entire AI industry