Track Hyper | Comparable to CoWoS: Intel Breaks Through Advanced Packaging Technology

Author: Zhou Yuan / Wall Street Insight

Since the new CEO Chen Liwu took office, Intel's fundamentals seem to be increasingly solid, and new technologies have made significant progress.

Recently, Intel disclosed several breakthroughs in chip packaging technology at the Electronic Components Technology Conference (ECTC), particularly EMIB-T, which is used to enhance chip packaging size and power supply capabilities to support new technologies such as HBM4/4e.

Additionally, there are new dispersed heat sink designs and new thermal bonding technologies that can improve reliability and yield, supporting finer inter-chip connections.

EMIB-T (Embedded Multi-die Interconnect Bridge with TSV): is a major upgraded version of the embedded multi-chip interconnect bridging packaging technology, specifically designed for high-performance computing and heterogeneous integration.

The technological upgrades of EMIB-T focus mainly on three aspects: the introduction of TSV vertical interconnects, integration of high-power MIM capacitors, and an increase in packaging size and integration density.

First, by embedding Through-Silicon Vias (TSV) in the traditional EMIB silicon bridge structure, vertical signal transmission between multiple chips is achieved.

Compared to the cantilever power supply path of traditional EMIB, TSV supplies power directly from the bottom of the package, reducing power transmission resistance by more than 30%, significantly decreasing voltage drop and signal noise.

This design enables stable support for the power supply requirements of high-bandwidth memory such as HBM4 and HBM4e, while being compatible with UCIe-A interconnect technology, with data transfer rates reaching 32 Gb/s+.

Second, to address electromagnetic interference issues in high-speed signal transmission, EMIB-T integrates high-density Metal-Insulator-Metal (MIM) capacitors within the bridge, effectively suppressing power noise and ensuring signal integrity.

This innovation allows EMIB-T to maintain stable communication performance in complex heterogeneous systems, making it particularly suitable for scenarios with high signal quality requirements, such as AI accelerators and data center processors.

Third, EMIB-T supports a maximum packaging size of 120x180 millimeters, with a single package capable of integrating over 38 bridges and 12 rectangular bare dies, with bump pitch already achieved at 45 microns, and plans to further reduce it to 35 microns or even 25 microns in the future.

This high-density integration capability provides a more flexible architecture for Chiplet design, such as integrating CPU, GPU, HBM memory, and AI acceleration modules within a single package, significantly enhancing system-level performance.

This new technology will be owned by Intel Foundry.

Intel Foundry aims to leverage cutting-edge process node technology to manufacture chips for both Intel's internal and external companies.

Modern processors increasingly adopt complex heterogeneous designs, integrating various types of computing and memory components into a single chip package, thereby enhancing performance, cost, and energy efficiency.

These chip designs rely on increasingly complex advanced packaging technologies, which are the cornerstone of heterogeneous design.

Therefore, to keep pace with competitors like TSMC, Intel must continuously advance the research and development process of new chip technologies Intel's EMIB-T technology was initially released in May with Intel's Direct Connect, integrating Through-Silicon Vias (TSV) into the widely used EMIB technology—a silicon bridge embedded in the packaging substrate that provides communication and power pathways between chips/dies.

EMIB-T continues the advantages of traditional EMIB's 2.5D packaging (such as flexible chip layouts) while moving closer to 3D packaging (like Foveros) through TSV.

The vertical interconnect path of TSV shortens by over 50% compared to traditional packaging routing, enhancing data transmission rates (with bandwidth improvement of about 20%) and reducing communication latency (with latency reduction of about 15%).

This hybrid architecture allows EMIB-T to achieve high-density integration at larger chip sizes, providing critical support for future heterogeneous computing platforms.

At the same time, the use of TSV also enhances the communication bandwidth between chips, enabling the integration of high-speed HBM4/4e memory packaging, while using UCIe-A interconnect technology increases data transmission rates to over 32 Gb/s.

EMIB-T supports organic substrates and glass substrates, with the latter achieving finer interconnections (such as 25-micron bump pitch) and more efficient signal transmission due to higher flatness and thermal stability, which is a key direction of Intel's future packaging strategy.

To complement Intel's simultaneous launch of the decomposed heat sink technology, EMIB-T can reduce the solder gap of thermal interface materials (TIM) by 25% and supports integrated microchannel heat sinks, suitable for chip packaging with thermal design power (TDP) of up to 1000W, addressing the heat dissipation challenges in high-performance computing.

This indicates that Intel is addressing chip heat dissipation issues from multiple angles.

The new thermal compression bonding process enhances the manufacturing yield and reliability of large packaging substrates by minimizing thermal differences, further strengthening the industrial deployment capability of EMIB-T.

The core goal of EMIB-T is to meet the demands of HBM4 memory and UCIe interconnects, making it an ideal packaging solution for AI accelerators, data center processors, and supercomputing chips.

Through the synergy of TSV power supply and MIM capacitors, EMIB-T can stably support HBM4's 3.2 TB/s bandwidth, providing efficient memory access capabilities for large model training and inference.

As the semiconductor industry transitions to Chiplet design, EMIB-T provides a unified packaging platform for multi-sourced chips (such as Intel CPUs, third-party GPUs, and memory).

This not only reduces R&D risks for customers but also enhances system-level energy efficiency through high-density interconnects and low-power designs. Currently, companies like AWS and Cisco have partnered with Intel to apply EMIB-T in next-generation servers and networking devices.

The launch of EMIB-T marks Intel's efforts to catch up technologically in the advanced packaging field.

Compared to TSMC's CoWoS, EMIB-T has advantages in power integrity and signal stability, while derivative technologies like Foveros-R and Foveros-B (which use re-routing layers and bridge chips in packaging) further expand its application scenarios In addition, Siemens EDA has launched a TSV-based EMIB-T reference flow, building a complete toolchain from thermal analysis to signal integrity, accelerating the commercialization of this technology.

Chen Liwu's efforts go beyond advancing Intel's new packaging technology; his more "sincere" open strategy—providing packaging services for chips that do not use any Intel-manufactured components—helps Intel's chip manufacturing services establish relationships with potential new customers.

Intel plans to achieve mass production of EMIB-T packaging in the second half of 2025 and gradually reduce the bump pitch from 45 microns to 25 microns to support higher density chip integration.

With the maturity of glass substrate technology, EMIB-T is expected to achieve integration of more than 24 HBM in a single package by 2028, further driving breakthroughs in memory bandwidth.

This technology is not only an important part of Intel's foundry strategy but will also have a profound impact on the development direction of global semiconductor packaging technology